'Near zero-cost memory expansion through recycling'

Meta recycled retired DDR4 memory instead of purchasing expensive new DRAM

CXL technology turned discarded server memory into useful computing capacity

Meta reported 25% fewer servers for machine learning inference workloads

Memory shortages, rising DRAM prices, and extended delivery schedules have pushed hyperscalers toward alternatives that seemed impractical only recently, but Meta has developed a way to reuse old DDR4 memory pulled from decommissioned servers rather than discarding it.

The approach allows companies to expand server memory capacity without purchasing new DRAM, a cost researchers describe as the so-called RAM tax.

This expansion is made possible through Compute Express Link technology (CXL), which connects the older DDR4 modules alongside newer DDR5 memory pools on the same machine.

Reusing old memory instead of buying new memory

Meta describes the approach as delivering near-zero-cost memory expansion while also reducing electronic waste and infrastructure emissions considerably.

The strategy arrives at a time when memory supply constraints continue affecting server deployment schedules across cloud computing environments worldwide.

According to Meta researchers, existing CXL implementations struggled because expanded memory delivered nearly ten times lower bandwidth than local memory.

The company also reported approximately 60% higher latency levels compared with directly attached memory residing alongside processor sockets inside servers.

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Another limitation involved commercial CXL products bundling controllers with DRAM modules, preventing practical reuse of existing DDR4 inventories at scale.

Meta responded by developing an internal ASIC known as Vistara, specifically engineered around low latency, power efficiency and recycled memory usage.

The accompanying software stack automatically determines suitable memory ratios for individual workloads while disabling expansion where delays become unacceptable operational compromises.

"We address these challenges via hardware–software co-design. On the hardware side, we design an in-house CXL ASIC, Vistara, optimized for DRAM reuse, power efficiency, and low latency,” Meta said.

“On the software side, we build an optimized solution based on TPP (Transparent Page Placement), determine the appropriate local-to-expanded memory ratio for each workload, and automate per-workload configuration, including disabling expanded memory for workloads that cannot tolerate the increased latency."

Meta claims the architecture demonstrates sufficient practical value to justify deployment in production environments that handle diverse computational requirements daily.

Meta reported that disaggregated machine learning inference workloads achieved server count reductions reaching as high as 25% through implementation.

Distributed cache systems reportedly recorded average latency reductions of about 29%, despite relying partly upon slower recycled memory resources underneath.

The findings suggest that additional capacity sometimes outweighs raw memory speed when applications struggle more with shortages than response times.

Interestingly, the same interconnect technology attracting Meta's attention is also drawing interest from semiconductor firms developing large accelerator fabrics globally.

The broader ecosystem includes work from companies pursuing alternatives to proprietary interconnect technologies such as Nvidia's widely adopted NVLink systems.

Among these is Ultra Accelerator Link, or UAL, a separate initiative backed by AMD, AWS, Google, Microsoft and Meta to connect accelerators across different hardware vendors.

Within Meta's own testing, disaggregated machine learning inference systems and distributed caching infrastructure were the two workloads examined directly by researchers.

Both recorded measurable improvements from the recycled memory approach, with inference systems requiring fewer servers and caches experiencing lower average latency.

Whether recycled DDR4 through CXL becomes standard practice will likely depend on performance trade-offs remaining acceptable outside hyperscale environments.

Via Blocksandfiles

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